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rtl2832-tuner_e4k.h
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1#ifndef _E4K_TUNER_H
2#define _E4K_TUNER_H
3
4#include "rtl2832.h"
5
6 namespace RTL2832_NAMESPACE { namespace TUNERS_NAMESPACE {
7
8 class e4k;
9
10} } // TUNERS_NAMESPACE // RTL2832_NAMESPACE
11
12///////////////////////////////////////////////////////////////////////////////
13
14/* (C) 2011-2012 by Harald Welte <laforge@gnumonks.org>
15 *
16 * All Rights Reserved
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 3 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program. If not, see <http://www.gnu.org/licenses/>.
30 */
31
32 enum e4k_reg {
33 E4K_REG_MASTER1 = 0x00,
34 E4K_REG_MASTER2 = 0x01,
35 E4K_REG_MASTER3 = 0x02,
36 E4K_REG_MASTER4 = 0x03,
37 E4K_REG_MASTER5 = 0x04,
38 E4K_REG_CLK_INP = 0x05,
39 E4K_REG_REF_CLK = 0x06,
40 E4K_REG_SYNTH1 = 0x07,
41 E4K_REG_SYNTH2 = 0x08,
42 E4K_REG_SYNTH3 = 0x09,
43 E4K_REG_SYNTH4 = 0x0a,
44 E4K_REG_SYNTH5 = 0x0b,
45 E4K_REG_SYNTH6 = 0x0c,
46 E4K_REG_SYNTH7 = 0x0d,
47 E4K_REG_SYNTH8 = 0x0e,
48 E4K_REG_SYNTH9 = 0x0f,
49 E4K_REG_FILT1 = 0x10,
50 E4K_REG_FILT2 = 0x11,
51 E4K_REG_FILT3 = 0x12,
52 // gap
53 E4K_REG_GAIN1 = 0x14,
54 E4K_REG_GAIN2 = 0x15,
55 E4K_REG_GAIN3 = 0x16,
56 E4K_REG_GAIN4 = 0x17,
57 // gap
58 E4K_REG_AGC1 = 0x1a,
59 E4K_REG_AGC2 = 0x1b,
60 E4K_REG_AGC3 = 0x1c,
61 E4K_REG_AGC4 = 0x1d,
62 E4K_REG_AGC5 = 0x1e,
63 E4K_REG_AGC6 = 0x1f,
64 E4K_REG_AGC7 = 0x20,
65 E4K_REG_AGC8 = 0x21,
66 // gap
67 E4K_REG_AGC11 = 0x24,
68 E4K_REG_AGC12 = 0x25,
69 // gap
70 E4K_REG_DC1 = 0x29,
71 E4K_REG_DC2 = 0x2a,
72 E4K_REG_DC3 = 0x2b,
73 E4K_REG_DC4 = 0x2c,
74 E4K_REG_DC5 = 0x2d,
75 E4K_REG_DC6 = 0x2e,
76 E4K_REG_DC7 = 0x2f,
77 E4K_REG_DC8 = 0x30,
78 // gap
79 E4K_REG_QLUT0 = 0x50,
80 E4K_REG_QLUT1 = 0x51,
81 E4K_REG_QLUT2 = 0x52,
82 E4K_REG_QLUT3 = 0x53,
83 // gap
84 E4K_REG_ILUT0 = 0x60,
85 E4K_REG_ILUT1 = 0x61,
86 E4K_REG_ILUT2 = 0x62,
87 E4K_REG_ILUT3 = 0x63,
88 // gap
89 E4K_REG_DCTIME1 = 0x70,
90 E4K_REG_DCTIME2 = 0x71,
91 E4K_REG_DCTIME3 = 0x72,
92 E4K_REG_DCTIME4 = 0x73,
93 E4K_REG_PWM1 = 0x74,
94 E4K_REG_PWM2 = 0x75,
95 E4K_REG_PWM3 = 0x76,
96 E4K_REG_PWM4 = 0x77,
97 E4K_REG_BIAS = 0x78,
98 E4K_REG_CLKOUT_PWDN = 0x7a,
99 E4K_REG_CHFILT_CALIB = 0x7b,
100 E4K_REG_I2C_REG_ADDR = 0x7d,
101 // FIXME
102};
103
104#define E4K_MASTER1_RESET (1 << 0)
105#define E4K_MASTER1_NORM_STBY (1 << 1)
106#define E4K_MASTER1_POR_DET (1 << 2)
107
108#define E4K_SYNTH1_PLL_LOCK (1 << 0)
109#define E4K_SYNTH1_BAND_SHIF 1
110
111#define E4K_SYNTH7_3PHASE_EN (1 << 3)
112
113#define E4K_SYNTH8_VCOCAL_UPD (1 << 2)
114
115#define E4K_FILT3_DISABLE (1 << 5)
116
117#define E4K_AGC1_LIN_MODE (1 << 4)
118#define E4K_AGC1_LNA_UPDATE (1 << 5)
119#define E4K_AGC1_LNA_G_LOW (1 << 6)
120#define E4K_AGC1_LNA_G_HIGH (1 << 7)
121
122#define E4K_AGC6_LNA_CAL_REQ (1 << 4)
123
124#define E4K_AGC7_MIX_GAIN_AUTO (1 << 0)
125#define E4K_AGC7_GAIN_STEP_5dB (1 << 5)
126
127#define E4K_AGC8_SENS_LIN_AUTO (1 << 0)
128
129#define E4K_AGC11_LNA_GAIN_ENH (1 << 0)
130
131#define E4K_DC1_CAL_REQ (1 << 0)
132
133#define E4K_DC5_I_LUT_EN (1 << 0)
134#define E4K_DC5_Q_LUT_EN (1 << 1)
135#define E4K_DC5_RANGE_DET_EN (1 << 2)
136#define E4K_DC5_RANGE_EN (1 << 3)
137#define E4K_DC5_TIMEVAR_EN (1 << 4)
138
139#define E4K_CLKOUT_DISABLE 0x96
140
141#define E4K_CHFCALIB_CMD (1 << 0)
142
143#define E4K_AGC1_MOD_MASK 0xF
144
145 enum e4k_agc_mode {
146 E4K_AGC_MOD_SERIAL = 0x0,
147 E4K_AGC_MOD_IF_PWM_LNA_SERIAL = 0x1,
148 E4K_AGC_MOD_IF_PWM_LNA_AUTONL = 0x2,
149 E4K_AGC_MOD_IF_PWM_LNA_SUPERV = 0x3,
150 E4K_AGC_MOD_IF_SERIAL_LNA_PWM = 0x4,
151 E4K_AGC_MOD_IF_PWM_LNA_PWM = 0x5,
152 E4K_AGC_MOD_IF_DIG_LNA_SERIAL = 0x6,
153 E4K_AGC_MOD_IF_DIG_LNA_AUTON = 0x7,
154 E4K_AGC_MOD_IF_DIG_LNA_SUPERV = 0x8,
155 E4K_AGC_MOD_IF_SERIAL_LNA_AUTON = 0x9,
156 E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV = 0xa,
157};
158
159 enum e4k_band {
160 E4K_BAND_VHF2 = 0,
161 E4K_BAND_VHF3 = 1,
162 E4K_BAND_UHF = 2,
163 E4K_BAND_L = 3,
164};
165
166 enum e4k_mixer_filter_bw {
167 E4K_F_MIX_BW_27M = 0,
168 E4K_F_MIX_BW_4M6 = 8,
169 E4K_F_MIX_BW_4M2 = 9,
170 E4K_F_MIX_BW_3M8 = 10,
171 E4K_F_MIX_BW_3M4 = 11,
172 E4K_F_MIX_BW_3M = 12,
173 E4K_F_MIX_BW_2M7 = 13,
174 E4K_F_MIX_BW_2M3 = 14,
175 E4K_F_MIX_BW_1M9 = 15,
176};
177
178 enum e4k_if_filter {
179 E4K_IF_FILTER_MIX,
180 E4K_IF_FILTER_CHAN,
181 E4K_IF_FILTER_RC
182};
183 struct e4k_pll_params {
184 uint32_t fosc;
185 uint32_t intended_flo;
186 uint32_t flo;
187 uint16_t x;
188 uint8_t z;
189 uint8_t r;
190 uint8_t r_idx;
191 uint8_t threephase;
192};
193
194 struct e4k_state {
195 RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k* pTuner;
196 uint8_t i2c_addr;
197 enum e4k_band band;
198 struct e4k_pll_params vco;
199};
200
201///////////////////////////////////////////////////////////////////////////////
202
203/* structure describing a field in a register */
204 struct reg_field {
205 uint8_t reg;
206 uint8_t shift;
207 uint8_t width;
208};
209
210 struct reg_field_ops {
211 const struct reg_field *fields;
212 const char **field_names;
213 uint32_t num_fields;
214 void *data;
215 int (*write_cb)(void *data, uint32_t reg, uint32_t val);
216 uint32_t (*read_cb)(void *data, uint32_t reg);
217};
218
219 enum cmd_op {
220 CMD_OP_GET = (1 << 0),
221 CMD_OP_SET = (1 << 1),
222 CMD_OP_EXEC = (1 << 2),
223};
224
225uint32_t reg_field_read(struct reg_field_ops *ops, struct reg_field *field);
226 int reg_field_write(struct reg_field_ops *ops, struct reg_field *field, uint32_t val);
227 int reg_field_cmd(struct cmd_state *cs, enum cmd_op op,
228 const char *cmd, int argc, char **argv,
229 struct reg_field_ops *ops);
230
231///////////////////////////////////////////////////////////////////////////////
232
233 int e4k_init(struct e4k_state *e4k, bool enable_dc_offset_loop = true, bool set_manual_gain = false);
234 int e4k_if_gain_set(struct e4k_state *e4k, uint8_t stage, int8_t value);
235 int e4k_mixer_gain_set(struct e4k_state *e4k, int8_t value);
236 int e4k_commonmode_set(struct e4k_state *e4k, int8_t value);
237 int e4k_tune_freq(struct e4k_state *e4k, uint32_t freq);
238 int e4k_tune_params(struct e4k_state *e4k, struct e4k_pll_params *p);
239 int e4k_compute_pll_params(struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo);
240 int e4k_if_filter_bw_get(struct e4k_state *e4k, enum e4k_if_filter filter);
241 int e4k_if_filter_bw_set(struct e4k_state *e4k, enum e4k_if_filter filter,
242 uint32_t bandwidth);
243 int e4k_if_filter_chan_enable(struct e4k_state *e4k, int on);
244 int e4k_rf_filter_set(struct e4k_state *e4k);
245/*
246 int e4k_reg_write(struct e4k_state *e4k, uint8_t reg, uint8_t val);
247 int e4k_reg_read(struct e4k_state *e4k, uint8_t reg);
248*/
249 int sam3u_e4k_init(struct e4k_state *e4k, void *i2c, uint8_t slave_addr);
250 void sam3u_e4k_power(struct e4k_state *e4k, int on);
251 void sam3u_e4k_stby(struct e4k_state *e4k, int on);
252
253
254 int e4k_manual_dc_offset(struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange);
255 int e4k_dc_offset_calibrate(struct e4k_state *e4k);
256 int e4k_dc_offset_gen_table(struct e4k_state *e4k);
257
258///////////////////////////////////////////////////////////////////////////////
259
260 namespace RTL2832_NAMESPACE { namespace TUNERS_NAMESPACE {
261
262 class e4k : public RTL2832_NAMESPACE::tuner_skeleton
263{
264 IMPLEMENT_INLINE_TUNER_FACTORY(e4k)
265 public:
266 e4k(demod* p);
267 public:
268 inline virtual const char* name() const
269 { return "Elonics E4K"; }
270 public:
271 int initialise(tuner::PPARAMS params = NULL);
272 int set_frequency(double freq);
273 int set_bandwidth(double bw);
274 int set_gain(double gain);
275 int set_gain_mode(int mode);
276 int set_auto_gain_mode(bool on = true);
277 bool calc_appropriate_gain_mode(int& mode)/* const*/;
278 private:
279 int update_gain_mode();
280 public:
281 struct e4k_state m_stateE4K;
282};
283
284} } // TUNERS_NAMESPACE, RTL2832_NAMESPACE
285
286///////////////////////////////////////////////////////////////////////////////
287
288#define RTL2832_E4000_ADDITIONAL_INIT_REG_TABLE_LEN 34
289
290#define RTL2832_E4000_LNA_GAIN_TABLE_LEN 16
291#define RTL2832_E4000_LNA_GAIN_ADD_TABLE_LEN 8
292#define RTL2832_E4000_MIXER_GAIN_TABLE_LEN 2
293#define RTL2832_E4000_IF_STAGE_1_GAIN_TABLE_LEN 2
294#define RTL2832_E4000_IF_STAGE_2_GAIN_TABLE_LEN 4
295#define RTL2832_E4000_IF_STAGE_3_GAIN_TABLE_LEN 4
296#define RTL2832_E4000_IF_STAGE_4_GAIN_TABLE_LEN 4
297#define RTL2832_E4000_IF_STAGE_5_GAIN_TABLE_LEN 8
298#define RTL2832_E4000_IF_STAGE_6_GAIN_TABLE_LEN 8
299
300#define RTL2832_E4000_LNA_GAIN_BAND_NUM 2
301#define RTL2832_E4000_MIXER_GAIN_BAND_NUM 2
302
303#define RTL2832_E4000_RF_BAND_BOUNDARY_HZ 300000000
304
305#define RTL2832_E4000_LNA_GAIN_ADDR 0x14
306#define RTL2832_E4000_LNA_GAIN_MASK 0xf
307#define RTL2832_E4000_LNA_GAIN_SHIFT 0
308
309#define RTL2832_E4000_LNA_GAIN_ADD_ADDR 0x24
310#define RTL2832_E4000_LNA_GAIN_ADD_MASK 0x7
311#define RTL2832_E4000_LNA_GAIN_ADD_SHIFT 0
312
313#define RTL2832_E4000_MIXER_GAIN_ADDR 0x15
314#define RTL2832_E4000_MIXER_GAIN_MASK 0x1
315#define RTL2832_E4000_MIXER_GAIN_SHIFT 0
316
317#define RTL2832_E4000_IF_STAGE_1_GAIN_ADDR 0x16
318#define RTL2832_E4000_IF_STAGE_1_GAIN_MASK 0x1
319#define RTL2832_E4000_IF_STAGE_1_GAIN_SHIFT 0
320
321#define RTL2832_E4000_IF_STAGE_2_GAIN_ADDR 0x16
322#define RTL2832_E4000_IF_STAGE_2_GAIN_MASK 0x6
323#define RTL2832_E4000_IF_STAGE_2_GAIN_SHIFT 1
324
325#define RTL2832_E4000_IF_STAGE_3_GAIN_ADDR 0x16
326#define RTL2832_E4000_IF_STAGE_3_GAIN_MASK 0x18
327#define RTL2832_E4000_IF_STAGE_3_GAIN_SHIFT 3
328
329#define RTL2832_E4000_IF_STAGE_4_GAIN_ADDR 0x16
330#define RTL2832_E4000_IF_STAGE_4_GAIN_MASK 0x60
331#define RTL2832_E4000_IF_STAGE_4_GAIN_SHIFT 5
332
333#define RTL2832_E4000_IF_STAGE_5_GAIN_ADDR 0x17
334#define RTL2832_E4000_IF_STAGE_5_GAIN_MASK 0x7
335#define RTL2832_E4000_IF_STAGE_5_GAIN_SHIFT 0
336
337#define RTL2832_E4000_IF_STAGE_6_GAIN_ADDR 0x17
338#define RTL2832_E4000_IF_STAGE_6_GAIN_MASK 0x38
339#define RTL2832_E4000_IF_STAGE_6_GAIN_SHIFT 3
340
341#define RTL2832_E4000_TUNER_OUTPUT_POWER_UNIT_0P1_DBM -100
342
343#define RTL2832_E4000_TUNER_MODE_UPDATE_WAIT_TIME_MS 1000
344
345#endif /* _E4K_TUNER_H */
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k
Definition: rtl2832-tuner_e4k.h:263
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::set_frequency
int set_frequency(double freq)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::e4k
e4k(demod *p)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::name
virtual const char * name() const
Definition: rtl2832-tuner_e4k.h:268
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::set_gain
int set_gain(double gain)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::set_gain_mode
int set_gain_mode(int mode)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::initialise
int initialise(tuner::PPARAMS params=NULL)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::m_stateE4K
struct e4k_state m_stateE4K
Definition: rtl2832-tuner_e4k.h:281
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::set_auto_gain_mode
int set_auto_gain_mode(bool on=true)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::set_bandwidth
int set_bandwidth(double bw)
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k::calc_appropriate_gain_mode
bool calc_appropriate_gain_mode(int &mode)
RTL2832_NAMESPACE::demod
Definition: rtl2832.h:310
RTL2832_NAMESPACE::tuner_skeleton
Definition: rtl2832.h:187
RTL2832_NAMESPACE::tuner_skeleton::gain
virtual double gain() const
Definition: rtl2832.h:228
RTL2832_NAMESPACE
Definition: rtl2832-tuner_e4000.h:6
e4k_dc_offset_gen_table
int e4k_dc_offset_gen_table(struct e4k_state *e4k)
e4k_dc_offset_calibrate
int e4k_dc_offset_calibrate(struct e4k_state *e4k)
e4k_reg
e4k_reg
Definition: rtl2832-tuner_e4k.h:32
E4K_REG_AGC12
@ E4K_REG_AGC12
Definition: rtl2832-tuner_e4k.h:68
E4K_REG_AGC6
@ E4K_REG_AGC6
Definition: rtl2832-tuner_e4k.h:63
E4K_REG_DC1
@ E4K_REG_DC1
Definition: rtl2832-tuner_e4k.h:70
E4K_REG_DCTIME1
@ E4K_REG_DCTIME1
Definition: rtl2832-tuner_e4k.h:89
E4K_REG_QLUT2
@ E4K_REG_QLUT2
Definition: rtl2832-tuner_e4k.h:81
E4K_REG_SYNTH2
@ E4K_REG_SYNTH2
Definition: rtl2832-tuner_e4k.h:41
E4K_REG_DC4
@ E4K_REG_DC4
Definition: rtl2832-tuner_e4k.h:73
E4K_REG_SYNTH4
@ E4K_REG_SYNTH4
Definition: rtl2832-tuner_e4k.h:43
E4K_REG_AGC5
@ E4K_REG_AGC5
Definition: rtl2832-tuner_e4k.h:62
E4K_REG_SYNTH7
@ E4K_REG_SYNTH7
Definition: rtl2832-tuner_e4k.h:46
E4K_REG_PWM3
@ E4K_REG_PWM3
Definition: rtl2832-tuner_e4k.h:95
E4K_REG_GAIN4
@ E4K_REG_GAIN4
Definition: rtl2832-tuner_e4k.h:56
E4K_REG_REF_CLK
@ E4K_REG_REF_CLK
Definition: rtl2832-tuner_e4k.h:39
E4K_REG_DC7
@ E4K_REG_DC7
Definition: rtl2832-tuner_e4k.h:76
E4K_REG_MASTER3
@ E4K_REG_MASTER3
Definition: rtl2832-tuner_e4k.h:35
E4K_REG_ILUT3
@ E4K_REG_ILUT3
Definition: rtl2832-tuner_e4k.h:87
E4K_REG_GAIN1
@ E4K_REG_GAIN1
Definition: rtl2832-tuner_e4k.h:53
E4K_REG_SYNTH8
@ E4K_REG_SYNTH8
Definition: rtl2832-tuner_e4k.h:47
E4K_REG_ILUT2
@ E4K_REG_ILUT2
Definition: rtl2832-tuner_e4k.h:86
E4K_REG_DCTIME2
@ E4K_REG_DCTIME2
Definition: rtl2832-tuner_e4k.h:90
E4K_REG_GAIN3
@ E4K_REG_GAIN3
Definition: rtl2832-tuner_e4k.h:55
E4K_REG_MASTER5
@ E4K_REG_MASTER5
Definition: rtl2832-tuner_e4k.h:37
E4K_REG_AGC2
@ E4K_REG_AGC2
Definition: rtl2832-tuner_e4k.h:59
E4K_REG_SYNTH1
@ E4K_REG_SYNTH1
Definition: rtl2832-tuner_e4k.h:40
E4K_REG_ILUT1
@ E4K_REG_ILUT1
Definition: rtl2832-tuner_e4k.h:85
E4K_REG_DC3
@ E4K_REG_DC3
Definition: rtl2832-tuner_e4k.h:72
E4K_REG_PWM4
@ E4K_REG_PWM4
Definition: rtl2832-tuner_e4k.h:96
E4K_REG_AGC1
@ E4K_REG_AGC1
Definition: rtl2832-tuner_e4k.h:58
E4K_REG_FILT1
@ E4K_REG_FILT1
Definition: rtl2832-tuner_e4k.h:49
E4K_REG_MASTER4
@ E4K_REG_MASTER4
Definition: rtl2832-tuner_e4k.h:36
E4K_REG_QLUT1
@ E4K_REG_QLUT1
Definition: rtl2832-tuner_e4k.h:80
E4K_REG_DCTIME4
@ E4K_REG_DCTIME4
Definition: rtl2832-tuner_e4k.h:92
E4K_REG_AGC8
@ E4K_REG_AGC8
Definition: rtl2832-tuner_e4k.h:65
E4K_REG_AGC11
@ E4K_REG_AGC11
Definition: rtl2832-tuner_e4k.h:67
E4K_REG_DCTIME3
@ E4K_REG_DCTIME3
Definition: rtl2832-tuner_e4k.h:91
E4K_REG_CLK_INP
@ E4K_REG_CLK_INP
Definition: rtl2832-tuner_e4k.h:38
E4K_REG_AGC3
@ E4K_REG_AGC3
Definition: rtl2832-tuner_e4k.h:60
E4K_REG_CLKOUT_PWDN
@ E4K_REG_CLKOUT_PWDN
Definition: rtl2832-tuner_e4k.h:98
E4K_REG_FILT3
@ E4K_REG_FILT3
Definition: rtl2832-tuner_e4k.h:51
E4K_REG_SYNTH9
@ E4K_REG_SYNTH9
Definition: rtl2832-tuner_e4k.h:48
E4K_REG_CHFILT_CALIB
@ E4K_REG_CHFILT_CALIB
Definition: rtl2832-tuner_e4k.h:99
E4K_REG_QLUT0
@ E4K_REG_QLUT0
Definition: rtl2832-tuner_e4k.h:79
E4K_REG_I2C_REG_ADDR
@ E4K_REG_I2C_REG_ADDR
Definition: rtl2832-tuner_e4k.h:100
E4K_REG_SYNTH5
@ E4K_REG_SYNTH5
Definition: rtl2832-tuner_e4k.h:44
E4K_REG_BIAS
@ E4K_REG_BIAS
Definition: rtl2832-tuner_e4k.h:97
E4K_REG_PWM2
@ E4K_REG_PWM2
Definition: rtl2832-tuner_e4k.h:94
E4K_REG_AGC7
@ E4K_REG_AGC7
Definition: rtl2832-tuner_e4k.h:64
E4K_REG_DC6
@ E4K_REG_DC6
Definition: rtl2832-tuner_e4k.h:75
E4K_REG_QLUT3
@ E4K_REG_QLUT3
Definition: rtl2832-tuner_e4k.h:82
E4K_REG_SYNTH3
@ E4K_REG_SYNTH3
Definition: rtl2832-tuner_e4k.h:42
E4K_REG_ILUT0
@ E4K_REG_ILUT0
Definition: rtl2832-tuner_e4k.h:84
E4K_REG_MASTER1
@ E4K_REG_MASTER1
Definition: rtl2832-tuner_e4k.h:33
E4K_REG_PWM1
@ E4K_REG_PWM1
Definition: rtl2832-tuner_e4k.h:93
E4K_REG_GAIN2
@ E4K_REG_GAIN2
Definition: rtl2832-tuner_e4k.h:54
E4K_REG_AGC4
@ E4K_REG_AGC4
Definition: rtl2832-tuner_e4k.h:61
E4K_REG_SYNTH6
@ E4K_REG_SYNTH6
Definition: rtl2832-tuner_e4k.h:45
E4K_REG_FILT2
@ E4K_REG_FILT2
Definition: rtl2832-tuner_e4k.h:50
E4K_REG_DC2
@ E4K_REG_DC2
Definition: rtl2832-tuner_e4k.h:71
E4K_REG_DC5
@ E4K_REG_DC5
Definition: rtl2832-tuner_e4k.h:74
E4K_REG_DC8
@ E4K_REG_DC8
Definition: rtl2832-tuner_e4k.h:77
E4K_REG_MASTER2
@ E4K_REG_MASTER2
Definition: rtl2832-tuner_e4k.h:34
e4k_tune_freq
int e4k_tune_freq(struct e4k_state *e4k, uint32_t freq)
e4k_compute_pll_params
int e4k_compute_pll_params(struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo)
e4k_if_filter_bw_set
int e4k_if_filter_bw_set(struct e4k_state *e4k, enum e4k_if_filter filter, uint32_t bandwidth)
sam3u_e4k_power
void sam3u_e4k_power(struct e4k_state *e4k, int on)
e4k_rf_filter_set
int e4k_rf_filter_set(struct e4k_state *e4k)
sam3u_e4k_stby
void sam3u_e4k_stby(struct e4k_state *e4k, int on)
e4k_mixer_gain_set
int e4k_mixer_gain_set(struct e4k_state *e4k, int8_t value)
cmd_op
cmd_op
Definition: rtl2832-tuner_e4k.h:219
CMD_OP_GET
@ CMD_OP_GET
Definition: rtl2832-tuner_e4k.h:220
CMD_OP_SET
@ CMD_OP_SET
Definition: rtl2832-tuner_e4k.h:221
CMD_OP_EXEC
@ CMD_OP_EXEC
Definition: rtl2832-tuner_e4k.h:222
e4k_manual_dc_offset
int e4k_manual_dc_offset(struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange)
e4k_if_filter
e4k_if_filter
Definition: rtl2832-tuner_e4k.h:178
E4K_IF_FILTER_RC
@ E4K_IF_FILTER_RC
Definition: rtl2832-tuner_e4k.h:181
E4K_IF_FILTER_MIX
@ E4K_IF_FILTER_MIX
Definition: rtl2832-tuner_e4k.h:179
E4K_IF_FILTER_CHAN
@ E4K_IF_FILTER_CHAN
Definition: rtl2832-tuner_e4k.h:180
e4k_if_filter_bw_get
int e4k_if_filter_bw_get(struct e4k_state *e4k, enum e4k_if_filter filter)
e4k_init
int e4k_init(struct e4k_state *e4k, bool enable_dc_offset_loop=true, bool set_manual_gain=false)
reg_field_read
uint32_t reg_field_read(struct reg_field_ops *ops, struct reg_field *field)
reg_field_cmd
int reg_field_cmd(struct cmd_state *cs, enum cmd_op op, const char *cmd, int argc, char **argv, struct reg_field_ops *ops)
e4k_mixer_filter_bw
e4k_mixer_filter_bw
Definition: rtl2832-tuner_e4k.h:166
E4K_F_MIX_BW_4M2
@ E4K_F_MIX_BW_4M2
Definition: rtl2832-tuner_e4k.h:169
E4K_F_MIX_BW_2M7
@ E4K_F_MIX_BW_2M7
Definition: rtl2832-tuner_e4k.h:173
E4K_F_MIX_BW_27M
@ E4K_F_MIX_BW_27M
Definition: rtl2832-tuner_e4k.h:167
E4K_F_MIX_BW_3M
@ E4K_F_MIX_BW_3M
Definition: rtl2832-tuner_e4k.h:172
E4K_F_MIX_BW_4M6
@ E4K_F_MIX_BW_4M6
Definition: rtl2832-tuner_e4k.h:168
E4K_F_MIX_BW_2M3
@ E4K_F_MIX_BW_2M3
Definition: rtl2832-tuner_e4k.h:174
E4K_F_MIX_BW_1M9
@ E4K_F_MIX_BW_1M9
Definition: rtl2832-tuner_e4k.h:175
E4K_F_MIX_BW_3M8
@ E4K_F_MIX_BW_3M8
Definition: rtl2832-tuner_e4k.h:170
E4K_F_MIX_BW_3M4
@ E4K_F_MIX_BW_3M4
Definition: rtl2832-tuner_e4k.h:171
e4k_if_gain_set
int e4k_if_gain_set(struct e4k_state *e4k, uint8_t stage, int8_t value)
e4k_tune_params
int e4k_tune_params(struct e4k_state *e4k, struct e4k_pll_params *p)
e4k_agc_mode
e4k_agc_mode
Definition: rtl2832-tuner_e4k.h:145
E4K_AGC_MOD_IF_DIG_LNA_AUTON
@ E4K_AGC_MOD_IF_DIG_LNA_AUTON
Definition: rtl2832-tuner_e4k.h:153
E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV
@ E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV
Definition: rtl2832-tuner_e4k.h:156
E4K_AGC_MOD_IF_DIG_LNA_SERIAL
@ E4K_AGC_MOD_IF_DIG_LNA_SERIAL
Definition: rtl2832-tuner_e4k.h:152
E4K_AGC_MOD_IF_SERIAL_LNA_AUTON
@ E4K_AGC_MOD_IF_SERIAL_LNA_AUTON
Definition: rtl2832-tuner_e4k.h:155
E4K_AGC_MOD_IF_PWM_LNA_PWM
@ E4K_AGC_MOD_IF_PWM_LNA_PWM
Definition: rtl2832-tuner_e4k.h:151
E4K_AGC_MOD_IF_DIG_LNA_SUPERV
@ E4K_AGC_MOD_IF_DIG_LNA_SUPERV
Definition: rtl2832-tuner_e4k.h:154
E4K_AGC_MOD_IF_PWM_LNA_SERIAL
@ E4K_AGC_MOD_IF_PWM_LNA_SERIAL
Definition: rtl2832-tuner_e4k.h:147
E4K_AGC_MOD_IF_SERIAL_LNA_PWM
@ E4K_AGC_MOD_IF_SERIAL_LNA_PWM
Definition: rtl2832-tuner_e4k.h:150
E4K_AGC_MOD_IF_PWM_LNA_AUTONL
@ E4K_AGC_MOD_IF_PWM_LNA_AUTONL
Definition: rtl2832-tuner_e4k.h:148
E4K_AGC_MOD_SERIAL
@ E4K_AGC_MOD_SERIAL
Definition: rtl2832-tuner_e4k.h:146
E4K_AGC_MOD_IF_PWM_LNA_SUPERV
@ E4K_AGC_MOD_IF_PWM_LNA_SUPERV
Definition: rtl2832-tuner_e4k.h:149
sam3u_e4k_init
int sam3u_e4k_init(struct e4k_state *e4k, void *i2c, uint8_t slave_addr)
reg_field_write
int reg_field_write(struct reg_field_ops *ops, struct reg_field *field, uint32_t val)
e4k_if_filter_chan_enable
int e4k_if_filter_chan_enable(struct e4k_state *e4k, int on)
e4k_band
e4k_band
Definition: rtl2832-tuner_e4k.h:159
E4K_BAND_VHF3
@ E4K_BAND_VHF3
Definition: rtl2832-tuner_e4k.h:161
E4K_BAND_L
@ E4K_BAND_L
Definition: rtl2832-tuner_e4k.h:163
E4K_BAND_UHF
@ E4K_BAND_UHF
Definition: rtl2832-tuner_e4k.h:162
E4K_BAND_VHF2
@ E4K_BAND_VHF2
Definition: rtl2832-tuner_e4k.h:160
e4k_commonmode_set
int e4k_commonmode_set(struct e4k_state *e4k, int8_t value)
rtl2832.h
IMPLEMENT_INLINE_TUNER_FACTORY
#define IMPLEMENT_INLINE_TUNER_FACTORY(class_name)
Definition: rtl2832.h:77
TUNERS_NAMESPACE
#define TUNERS_NAMESPACE
Definition: rtl2832.h:66
RTL2832_NAMESPACE::tuner::params
Definition: rtl2832.h:145
e4k_pll_params
Definition: rtl2832-tuner_e4k.h:183
e4k_pll_params::intended_flo
uint32_t intended_flo
Definition: rtl2832-tuner_e4k.h:185
e4k_pll_params::r
uint8_t r
Definition: rtl2832-tuner_e4k.h:189
e4k_pll_params::z
uint8_t z
Definition: rtl2832-tuner_e4k.h:188
e4k_pll_params::flo
uint32_t flo
Definition: rtl2832-tuner_e4k.h:186
e4k_pll_params::r_idx
uint8_t r_idx
Definition: rtl2832-tuner_e4k.h:190
e4k_pll_params::fosc
uint32_t fosc
Definition: rtl2832-tuner_e4k.h:184
e4k_pll_params::threephase
uint8_t threephase
Definition: rtl2832-tuner_e4k.h:191
e4k_pll_params::x
uint16_t x
Definition: rtl2832-tuner_e4k.h:187
e4k_state
Definition: rtl2832-tuner_e4k.h:194
e4k_state::vco
struct e4k_pll_params vco
Definition: rtl2832-tuner_e4k.h:198
e4k_state::band
enum e4k_band band
Definition: rtl2832-tuner_e4k.h:197
e4k_state::i2c_addr
uint8_t i2c_addr
Definition: rtl2832-tuner_e4k.h:196
e4k_state::pTuner
RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k * pTuner
Definition: rtl2832-tuner_e4k.h:195
reg_field_ops
Definition: rtl2832-tuner_e4k.h:210
reg_field_ops::data
void * data
Definition: rtl2832-tuner_e4k.h:214
reg_field_ops::read_cb
uint32_t(* read_cb)(void *data, uint32_t reg)
Definition: rtl2832-tuner_e4k.h:216
reg_field_ops::field_names
const char ** field_names
Definition: rtl2832-tuner_e4k.h:212
reg_field_ops::num_fields
uint32_t num_fields
Definition: rtl2832-tuner_e4k.h:213
reg_field_ops::write_cb
int(* write_cb)(void *data, uint32_t reg, uint32_t val)
Definition: rtl2832-tuner_e4k.h:215
reg_field_ops::fields
const struct reg_field * fields
Definition: rtl2832-tuner_e4k.h:211
reg_field
Definition: rtl2832-tuner_e4k.h:204
reg_field::width
uint8_t width
Definition: rtl2832-tuner_e4k.h:207
reg_field::shift
uint8_t shift
Definition: rtl2832-tuner_e4k.h:206
reg_field::reg
uint8_t reg
Definition: rtl2832-tuner_e4k.h:205